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In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SoC utilizing innovative process technology.
Key Qualifications
Minimum BS and 3+ years of relevant industry experience.
Recent successful tapeouts in deep submicron technology.
Knowledgeable in partition level P&R implementation including floorplanning, clock & power distribution, timing closure, and physical & electrical verification.
Strong knowledge of PD construction & analysis flows and methodology.
Shown ability to execute to stringent schedule & die size requirements.
Strong interpersonal skills.
Experienced in industry standard tools, understand their capabilities and underlying algorithms.
Description
Work with the logic design team to understand partition architecture and drive physical aspects early in the design cycle.
Complete netlist to GDS2 implementation for partition(s) meeting schedule and design goals.
Timing, physical and electrical verification, and driving the signoff closure for the partitions.
Resolve and improve design and flow issues related to physical design, identify potential solutions, and drive execution.
Drive optimization of PnR partitions, to achieve best Power/Performance/Area.
Education & Experience
Minimum BS and 3+ years of relevant industry experience.
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