Minimum qualifications:
- Bachelor's degree in Electrical Engineering or equivalent practical experience.
- 2 years of experience in ASIC design flows and methodologies, with 1 year of experience in IP integration (e.g., subsystems, memories, IO's and Analog IP) and RTL design.
- Experience in scripting languages (e.g., Python, Tcl, or Perl) and with Verilog/System Verilog.
- Experience working on various technologies (e.g., embedded processors, DDR, SerDes, networking-on-chip fabrics, etc.).
Preferred qualifications:
- Experience with ASIC design methodologies for clock domain checks, reset checks and low power design.
- Experience with silicon, emulation, FPGA validation and debug, functional verification, physical design, and DFT methodologies.
- Experience with SOC implementation standards and interfaces.
- Experience with low power design techniques, power gating, multi-voltage designs.
- Experience with industry standard integration tools.
- Experience on recent technology nodes.
About the job
Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
You will join a team working on SoC-level RTL design for data center accelerators. In this role you will own top-level RTL and integration of ASIC designs. In this role, you will work cross-functionally and will require interactions with numerous ASIC development teams. You will own deliverables to the cross-functional teams (e.g., Physical Design, Verification, Validation, etc.) at various project milestones. You will also be directly involved in defining and creating methodologies that enable an efficient design environment for ASIC engineers.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
The US base salary range for this full-time position is $127,000-$187,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.
Responsibilities
- Own the planning, creation, and delivery of top-level RTL/deliverables for ASIC and SOC projects from concept to working silicon volume.
- Resolve structural or functional issues related to the integration of ASICs and SOCs and collaborate with teams across Google to develop ideas for Silicon and hardware projects.
- Manage cross-functional interactions related to top-level RTL of chip projects.
- Improve cross-functional implementation methodologies to create consistency and efficiency across multiple parallel implementation teams and projects.
- Perform technical evaluations of vendors and IP, providing recommendations and assessment of process node tradeoffs to meet performance, power, area/cost goals.
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